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of an array of doubles. On lines 10 and 13, one must specify the size of
the memory operand. Otherwise the assembler would not know whether the
memory operand was a float (dword) or a double (qword).
FSUB src ST0 -= src. The src may be any coprocessor register
or a single or double precision number in memory.
FSUBR src ST0 = src - ST0. The src may be any coproces-
sor register or a single or double precision number in
memory.
FSUB dest, ST0 dest -= ST0. The dest may be any coprocessor reg-
ister.
FSUBR dest, ST0 dest = ST0 - dest. The dest may be any copro-
cessor register.
FSUBP dest or dest -= ST0then pop stack. The dest may be any
FSUBP dest, STO coprocessor register.
FSUBRP dest or dest = ST0 - dest then pop stack. The dest may
FSUBRP dest, STO be any coprocessor register.
FISUB src ST0 -= (float) src. Subtracts an integer from
ST0. The src must be a word or double word in mem-
ory.
FISUBR src ST0 = (float) src - ST0. SubtractsST0from an
integer. The src must be a word or double word in
memory.
128 CHAPTER 6. FLOATING POINT
Multiplication and division
The multiplication instructions are completely analogous to the addition
instructions.
FMUL src ST0 *= src. The src may be any coprocessor register
or a single or double precision number in memory.
FMUL dest, ST0 dest *= ST0. The dest may be any coprocessor reg-
ister.
FMULP dest or dest *= ST0then pop stack. The dest may be any
FMULP dest, STO coprocessor register.
FIMUL src ST0 *= (float) src. Multiplies an integer toST0.
The src must be a word or double word in memory.
Not surprisingly, the division instructions are analogous to the subtrac-
tion instructions. Division by zero results in an infinity.
FDIV src ST0 /= src. The src may be any coprocessor register
or a single or double precision number in memory.
FDIVR src ST0 = src / ST0. The src may be any coproces-
sor register or a single or double precision number in
memory.
FDIV dest, ST0 dest /= ST0. The dest may be any coprocessor reg-
ister.
FDIVR dest, ST0 dest = ST0 / dest. The dest may be any copro-
cessor register.
FDIVP dest or dest /= ST0then pop stack. The dest may be any
FDIVP dest, STO coprocessor register.
FDIVRP dest or dest = ST0 / dest then pop stack. The dest may
FDIVRP dest, STO be any coprocessor register.
FIDIV src ST0 /= (float) src. Divides ST0 by an integer.
The src must be a word or double word in memory.
FIDIVR src ST0 = (float) src / ST0. Divides an integer by
ST0. The src must be a word or double word in mem-
ory.
Comparisons
The coprocessor also performs comparisons of floating point numbers.
TheFCOMfamily of instructions does this operation.
6.3. THE NUMERIC COPROCESSOR 129
1 ; if ( x > y )
2 ;
3 fld qword [x] ; ST0 = x
4 fcomp qword [y] ; compare STO and y
5 fstsw ax ; move C bits into FLAGS
6 sahf
7 jna else_part ; if x not above y, goto else_part
8 then_part:
9 ; code for then part
10 jmp end_if
11 else_part:
12 ; code for else part
13 end_if:
Figure 6.6: Comparison example
FCOM src comparesST0andsrc. The src can be a coprocessor register
or a float or double in memory.
FCOMP src comparesST0andsrc, then pops stack. The src can be a
coprocessor register or a float or double in memory.
FCOMPP comparesST0andST1, then pops stack twice.
FICOM src comparesST0and(float) src. The src can be a word or
dword integer in memory.
FICOMP src comparesST0and(float)src, then pops stack. The src
can be a word or dword integer in memory.
FTST comparesST0and 0.
These instructions change the C0, C1, C2 and C3 bits of the coprocessor
status register. Unfortunately, it is not possible for the CPU to access these
bits directly. The conditional branch instructions use the FLAGS register,
not the coprocessor status register. However, it is relatively simple to trans-
fer the bits of the status word into the corresponding bits of the FLAGS
register using some new instructions:
FSTSW dest Stores the coprocessor status word into either a word in mem-
ory or the AX register.
SAHF Stores the AH register into the FLAGS register.
LAHF Loads the AH register with the bits of the FLAGS register.
Figure 6.6 shows a short example code snippet. Lines 5 and 6 transfer
the C0, C1, C2 and C3 bits of the coprocessor status word into the FLAGS
register. The bits are transfered so that they are analogous to the result
of a comparison of two unsigned integers. This is why line 7 uses aJNA
instruction.
130 CHAPTER 6. FLOATING POINT
The Pentium Pro (and later processors (Pentium II and III)) support two
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